1. Field of the Invention
The present invention relates to a semiconductor integrated circuit. More specifically, the present invention relates to a semiconductor integrated circuit including a plurality of semiconductor element groups each having prescribed function, and first, second and third interconnection patterns stacked successively on the plurality of semiconductor element groups.
2. Description of the Background Art
In a semiconductor memory of mega bit order, especially in dynamic random access memories (hereinafter referred to as DRAMs), memory array architecture employing two layers of aluminum interconnection patterns Al1 and Al2 is dominant, as described in ESSCIRC PROCEEDINGS, September 1991 pp. 21-24.
FIG. 25 is a block diagram showing a structure of a conventional DRAM chip. Referring to the figure, the DRAM chip includes a plurality of memory array regions 31 and peripheral circuit region 32 provided between the memory array regions. Each memory array region 31 includes a plurality of sub arrays 33 arranged in the row direction, a plurality of sense amplifier bands 34 provided between and at opposite ends of sub arrays 33, a row decoder 35 and a column decoder 36. Peripheral circuit region 32 includes a plurality of NAND gates, NOR gates and the like.
The DRAM chip is, specifically, formed of a silicon substrate, a plurality of transistors and capacitors formed on the surface of the silicon substrate, and an interconnection pattern W of metal having high melting point and aluminum interconnection patterns Al1 and Al2 stacked successively thereon.
FIG. 26 shows an example of a specific structure of the memory array region 31 of the DRAM chip shown in FIG. 25, which is a partial plan view showing the configuration of the sub array 33 and sense amplifier band 34. Referring to the figure, sub array 33 employs folded bit line structure and includes a plurality of memory cells MC arranged in the directions of rows and columns, and sense amplifier band 34 includes a plurality of sense amplifiers 34a provided corresponding to respective columns. In this region, the first layer of the high melting point metal interconnection pattern W is used as bit lines BL and /BL for connecting memory cells MC of each column to a sense amplifier 34a. The second layer, that is, the aluminum interconnection pattern Al1 is used as a part of a word line WL, and serves as a shunt for reducing time constant of the word line WL. The third layer, that is, the aluminum interconnection pattern Al2 is used as a column selection line CSL for transmitting an output from column decoder 36.
Bit lines BL and /BL are formed of the interconnection pattern W of metal having high melting point, in order to prevent migration of the material of bit lines BL and /BL to the silicon substrate. As the metal having high melting point, tungsten silicide (WSi) is used, as an example.
Though bit lines BL and /BL must have low resistance so as to increase the speed of data reading, what is more desirable is to reduce capacitance of the bit lines BL and /BL themselves to reduce power consumption, to increase the amount of read signal from memory cell MC so as to ensure operation margin, and to reduce capacitance between bit lines BL and /BL to reduce noise between bit lines BL and /BL, and therefore bit lines BL and /BL, that is, the interconnection pattern W of metal having high melting point, is made thin.
FIG. 27 shows an example of a specific structure of peripheral circuit region 32 of the DRAM chip shown in FIG. 25, and it is a partial plan view showing the layout of an area including a 2-input CMOS-NAND gate (hereinafter simply referred to as an NAND gate). FIG. 28 is an enlarged view of a main portion of FIG. 27. Referring to the figure, the NAND gate includes P channel MOS transistors P1 and P2 and N channel MOS transistors N1 and N2 arranged in two rows and two columns, and each of the transistors P1, P2, N1 and N2 includes a gate G extending in the Y direction in the figure and a source S and a drain D provided at opposing sides thereof. At one end of the gate G of each of the transistors P1, P2, N1 and N2, there is provided a pad PD, and pads PD of P channel MOS transistors P1 and P2 and pads PD of Nchannel MOS transistors N1 and N2 are provided adjacent to each other.
The third layer, that is, aluminum interconnection pattern Al2 used as the column selection line CSL in memory array region 31 is used in peripheral circuit region 32, as power supply lines VL and VLxe2x80x2 and signal lines SL1, SL2, . . . ; SL1xe2x80x2, SL2xe2x80x2, . . . , extending in the X direction in the figure. Power supply line VL is provided to cover a P region in which two P channel MOS transistors P1 and P2 are arranged, and to the power supply line VL, power supply potential Vcc (H level) is applied. Power supply line VLxe2x80x2 is provided to cover an N region in which two N channel MOS transistors N1 and N2. are arranged, and to the power supply line VLxe2x80x2, power supply potential Vss (L level) is applied.
Signal lines SL1, SL2, . . . are provided outward from power supply line VL with a prescribed pitch therebetween, and these lines are used for signal input/output between the NAND gate portion and the outside. Signal lines SL1xe2x80x2, SL2xe2x80x2, . . . are provided outward from power supply line VLxe2x80x2 with a prescribed pitch, and they are used for signal input/output between the NAND gate and the outside.
The second layer, that is, the aluminum interconnection pattern Al1 used as the shunt of word line WL in memory array region 31 is used, in this region, as a local line LL for internal connection of NAND gate.
More specifically, P channel MOS transistors P1 and P2 have their sources connected to local lines LL2 and LL3, respectively, through contact holes CH, while local lines LL2 and LL3 are connected via through holes TH to power supply line VL. P channel MOS transistors P1 and P2 and N channel MOS transistor N1 have their drains D connected to local line LL4 through contact holes CH, and local line LL4 is connected to signal line SL1xe2x80x2, for example, via a through hole TH. Signal line SL1xe2x80x2 serves as an output signal line for the NAND gate.
The source S of N channel MOS transistor N1 and the drain D of N channel MOS transistor N2 are commonly connected to local line LL5 through contact holes CH. N channel MOS transistor N2 has its source connected to local line LL6 through a contact hole CH, and local line LL6 is connected to power supply line VLxe2x80x2 via a through hole TH.
P channel MOS transistor P1 and N channel MOS transistor N1 have their gates G commonly connected to local line LL1 through pads PD and contact holes CH, and local line LL1 is connected to signal line SL2, for example, via through hole TH. Signal line SL2 serves as one input signal line A of the NAND gate.
P channel MOS transistor P2 and N channel MOS transistor N2 have their gates G commonly connected to local line LL7 through pads PD and contact holes CH, and local line LL7 is connected to signal line CL3xe2x80x2, for example, via through hole TH. Signal line SL3xe2x80x2 serves as the other input signal line B of the NAND gate.
Transistors P1, P2, N1 and N2 constitute an electric circuit such as shown in FIG. 29, that is, a NAND gate generally represented by such signs as shown in FIG. 30.
In the conventional DRAM chip, the first layer, that is, the interconnection pattern W of metal having high melting point is used as bit lines BL and /BL in the memory array region 31, while it is hardly utilized in the peripheral circuit region 32. The reason for this is that the conventional interconnection pattern W of metal having high melting point which is formed of tungsten silicide (WSi) has high sheet resistance, resulting in significant signal delay when it is used as the local line LL for connecting transistors P1, P2, N1 and N2 between each other.
However, recently, interconnection pattern W of metal having high melting point having relatively small sheet resistance as compared with the conventional pattern has come to be available. Specific example of the material includes tungsten (W) and titanium silicide (TiSi). By using the interconnection pattern W of metal having high melting point formed of such material as the lines in peripheral circuit region 32, the problem of signal delay can be solved. Accordingly, a new layout utilizing the interconnection pattern W of metal having a high melting point, which has been used only as the bit lines BL and /BL in the prior art, becomes possible.
Therefore, an object of the present invention is to provide a semiconductor integrated circuit having higher degree of freedom in layout, smaller layout area, smaller resistance of power supply lines, and small coupling noise of signal lines.
Briefly stated, in the present invention, among first, second and third interconnection patterns stacked on a plurality of semiconductor element groups, the first interconnection pattern is used as a local lines for connecting semiconductor elements in each of the semiconductor element groups.
Therefore, according to the present invention, the second interconnection pattern which has been conventionally used as the local lines can be freely used as the lower layer signal lines or lower layer power supply lines, and the third interconnection patterns can be freely used as upper layer signal lines or upper layer power supply lines. This significantly increases the degree of freedom of layout, and reduces the layout area.
According to a preferred embodiment of the present invention, the second interconnection pattern is used as lower layer signal line for signal input/output between each of the semiconductor element groups and the outside, and the third interconnection pattern is used as upper layer power supply lines for applying a power supply potential to each of the semiconductor element groups. More preferably, the second interconnection pattern is used as a contact electrode for connecting the upper layer power supply line and each of the semiconductor element groups.
According to another preferred embodiment of the present invention, the second interconnection pattern is used as lower layer power supply lines for applying the power supply potential to each of the semiconductor element groups, and the third interconnection pattern is used as upper layer signal lines for signal input/output between each of the semiconductor element groups and the outside. More preferably, the lower layer power supply line is provided to cover local lines. More preferably, the second interconnection pattern is further used as contact electrodes for connecting the upper layer signal lines and each of the semiconductor element groups.
According to a more preferred embodiment of the present invention, the second and third interconnection patterns are used as the lower and upper signal lines, respectively, for signal input/output between each of the semiconductor element groups and the outside. More preferably, the upper and lower signal lines are so provided that they do not at least partially overlap with each other.
According to a more preferred embodiment of the present invention, the second and third interconnection patterns are used as lower and upper power supply lines, respectively, for applying a power supply potential to each of the semiconductor element groups.
According to a still further preferred embodiment of the present invention, the first, second and third interconnection patterns are formed of aluminum.
According to a still further preferred embodiment of the present invention, the first interconnection pattern is formed of a metal having high melting point such as tungsten, and the second and third interconnection patterns are formed of aluminum.
According to a still further preferred embodiment of the present invention, each of the plurality of semiconductor element groups includes a plurality of semiconductor elements of first and second conductivity types, and the first interconnection pattern connect the semiconductor elements of the first conductivity type between each other in each of the semiconductor element groups.
According to a still further preferred embodiment of the present invention, the semiconductor integrated circuit includes a plurality of memory cells arranged in rows and columns on a surface of a semiconductor substrate, and the first interconnection pattern is further used as bit lines provided corresponding to each of the memory cell columns.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.